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? 2006 microchip technology inc. ds21810e-page 1 mcp6271/1r/2/3/4/5 features ? gain bandwidth product: 2 mhz (typ.) ? supply current: i q = 170 a (typ.) ? supply voltage: 2.0v to 5.5v ? rail-to-rail input/output ? extended temperature range: ?40c to +125c ? available in single, dual and quad packages ? parts with chip select (cs ) -single ( mcp6273 ) -dual ( mcp6275 ) applications ? automotive ? portable equipment ? photodiode amplifier ? analog filters ? notebooks and pdas ? battery powered systems available tools ? spice macro model (at www.microchip.com) ? filterlab ? software (at www.microchip.com) description the microchip technology inc. mcp6271/1r/2/3/4/5 family of operational amplifiers (op amps) provide wide bandwidth for the current. this family has a 2 mhz gain bandwidth product (gbwp) and a 65 phase margin. this family also operates from a single supply voltage as low as 2.0v, while drawing 170 a (typ.) quiescent current. the mc p6271/1r/2/3/4/5 supports rail-to-rail input and output swing, with a common mode input voltage range of v dd +300mv to v ss ?300mv. this family of op amps is designed with microchip?s advanced cmos process. the mcp6275 has a chip select input (cs ) for dual op amps in an 8-pin package and is manufactured by cascading two op amps (the output of op amp a connected to the non-inverting input of op amp b). the cs input puts the device in low power mode. the mcp6271/1r/2/3/4/5 family operates over the extended temperature range of ?40c to +125c, with a power supply range of 2.0v to 5.5v. package types v in ? mcp6271 pdip, soic, msop v dd 1 2 3 4 8 7 6 5 - + nc nc nc v in + v ss v out + - -+ - + v in ? mcp6273 pdip, soic, msop v dd 1 2 3 4 8 7 6 5 - + nc cs nc v in + v ss v out v ina ? MCP6272 pdip, soic, msop v outb 1 2 3 4 8 7 6 5 v inb + v dd v outa v ina + v ss v inb ? - + - + v ina ? mcp6274 pdip, soic, tssop v ind ? 1 2 3 4 14 13 12 11 v ss v outd v outa v ina + v dd v ind + 5 6 7 10 9 8 - + - + + - - + v inb + v inc + v outc v inb ? v outb v inc ? v ina ? mcp6275 pdip, soic, msop v outb 1 2 3 4 8 7 6 5 cs v dd v outa /v inb + v ina + v ss v inb ? v ss mcp6273 sot-23-6 cs 1 2 3 6 5 4 v dd v out v in +v in ? - + v ss mcp6271 sot-23-5 1 2 3 5 4 v dd v out v in + v in ? - + v dd mcp6271r sot-23-5 1 2 3 5 4 v ss v out v in + v in ? 170 a, 2 mhz rail-to-rail op amp
mcp6271/1r/2/3/4/5 ds21810e-page 2 ? 2006 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? v dd ?v ss ........................................................................7.0v current at analog input pins (v in + and v in ?) ...............2 ma analog inputs (v in + and v in ?) ?? .. v ss ?1.0vtov dd +1.0v all other inputs and outputs .......... v ss ? 0.3v to v dd +0.3v difference input voltage ...................................... |v dd ?v ss | output short circuit current .................................continuous current at output and supply pins ............................30 ma storage temperature....................................?65c to +150c junction temperature (t j ) . .........................................+150c esd protection on all pins (hbm/mm) ................ 4 kv/400v ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rati ng only and functional operation of the device at those or any other conditions above those indicated in the operational listi ngs of this specification is not implied. exposure to maximu m rating conditions for extended periods may affect device reliability. ?? see section 4.1.2 ?input voltage and current limits? . dc electrical specifications electrical characteristics : unless otherwise indicated, t a = +25c, v dd = +2.0v to +5.5v, v ss = gnd, v cm =v dd /2, v out v dd /2, r l =10k to v dd /2 and cs is tied low. parameters sym min typ max units conditions input offset (note 1) input offset voltage v os ?3.0 ? +3.0 mv v cm = v ss input offset voltage (extended temperature) v os ?5.0 ? +5.0 mv t a = ?40c to +125c, v cm = v ss input offset temperature drift v os / t a ?1.7?v/ct a = ?40c to +125c, v cm = v ss power supply rejection ratio psrr 70 90 ? db v cm = v ss input bias current and impedance input bias current i b ? 1.0 ? pa note 2 at temperature i b ? 50 200 pa t a = +85c (note 2) at temperature i b ?2 5nat a = +125c (note 2) input offset current i os ? 1.0 ? pa note 3 common mode input impedance z cm ?10 13 ||6 ? ||pf note 3 differential input impedance z diff ?10 13 ||3 ? ||pf note 3 common mode (note 4) common mode input voltage range v cmr v ss ? 0.15 ? v dd +0.15 v v dd = 2.0v (note 5) v cmr v ss ? 0.30 ? v dd +0.30 v v dd = 5.5v (note 5) common mode rejection ratio cmrr 70 85 ? db v cm = ?0.3v to 2.5v, v dd = 5v (note 6) common mode rejection ratio cmrr 65 80 ? db v cm = ?0.3v to 5.3v, v dd = 5v (note 6) open-loop gain dc open-loop gain (large signal) a ol 90 110 ? db v out = 0.2v to v dd ? 0.2v, v cm =v ss (note 1) note 1: the mcp6275?s v cm for op amp b (pins v outa /v inb + and v inb ?) is v ss +100mv. 2: the current at the mcp6275?s v inb ? pin is specified by i b only. 3: this specification does not apply to the mcp6275?s v outa /v inb + pin. 4: the mcp6275?s v inb ? pin (op amp b) has a common mode input voltage range (v cmr ) of v ss + 100 mv to v dd ? 100 mv. cmrr is not measured for op amp b of the mcp6275. the mcp6275?s v outa /v inb + pin (op amp b) has a voltage range specified by v oh and v ol . 5: set by design and characterization. 6: does not apply to op amp b of the mcp6275.
? 2006 microchip technology inc. ds21810e-page 3 mcp6271/1r/2/3/4/5 ac electrical specifications temperature specifications output maximum output voltage swing v ol , v oh v ss +15 ? v dd ? 15 mv 0.5v output overdrive (note 4) output short circuit current i sc ?25?ma power supply supply voltage v dd 2.0 ? 5.5 v quiescent current per amplifier i q 100 170 240 a i o = 0 electrical characteristics : unless otherwise indicated, t a = +25c, v dd = +2.0v to +5.5v, v ss =gnd, v cm =v dd /2, v out v dd /2, r l =10k to v dd /2, c l = 60 pf and and cs is tied low. parameters sym min typ max units conditions ac response gain bandwidth product gbwp ? 2.0 ? mhz phase margin pm ? 65 ? g = +1 slew rate sr ? 0.9 ? v/s noise input noise voltage e ni ? 4.6 ? v p-p f = 0.1 hz to 10 hz input noise voltage density e ni ? 20 ? nv/ hz f = 1 khz input noise current density i ni ? 3?fa/ hz f = 1 khz electrical characteristics: unless otherwise indicated, v dd = +2.0v to +5.5v and v ss =gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a ?40 ? +125 c operating temperature range t a ?40 ? +125 c note storage temperature range t a ?65 ? +150 c thermal package resistances thermal resistance, 5l-sot-23 ja ?256?c/w thermal resistance, 6l-sot-23 ja ?230?c/w thermal resistance, 8l-pdip ja ?85?c/w thermal resistance, 8l-soic ja ?163?c/w thermal resistance, 8l-msop ja ?206?c/w thermal resistance, 14l-pdip ja ? 70 ? c/w thermal resistance, 14l-soic ja ? 120 ? c/w thermal resistance, 14l-tssop ja ? 100 ? c/w note: the junction temperature (t j ) must not exceed the absolute maximum specification of +150c. dc electrical specifi cations (continued) electrical characteristics : unless otherwise indicated, t a = +25c, v dd = +2.0v to +5.5v, v ss = gnd, v cm =v dd /2, v out v dd /2, r l =10k to v dd /2 and cs is tied low. parameters sym min typ max units conditions note 1: the mcp6275?s v cm for op amp b (pins v outa /v inb + and v inb ?) is v ss +100mv. 2: the current at the mcp6275?s v inb ? pin is specified by i b only. 3: this specification does not apply to the mcp6275?s v outa /v inb + pin. 4: the mcp6275?s v inb ? pin (op amp b) has a common mode input voltage range (v cmr ) of v ss + 100 mv to v dd ? 100 mv. cmrr is not measured for op amp b of the mcp6275. the mcp6275?s v outa /v inb + pin (op amp b) has a voltage range specified by v oh and v ol . 5: set by design and characterization. 6: does not apply to op amp b of the mcp6275.
mcp6271/1r/2/3/4/5 ds21810e-page 4 ? 2006 microchip technology inc. mcp6273/mcp6275 ch ip select (cs ) specifications figure 1-1: timing diagram for the chip select (cs ) pin on the mcp6273 and mcp6275. electrical characteristics : unless otherwise indicated, t a = +25c, v dd = +2.0v to +5.5v, v ss =gnd, v cm =v dd /2, v out v dd /2, r l =10k to v dd /2, c l = 60 pf and and cs is tied low. parameters sym min typ max units conditions cs low specifications cs logic threshold, low v il v ss ?0.2v dd v cs input current, low i csl ?0.01? acs = v ss cs high specifications cs logic threshold, high v ih 0.8v dd ?v dd v cs input current, high i csh ?0.7 2 acs = v dd gnd current per amplifier i ss ? ?0.7 ? a cs = v dd amplifier output leakage ? ? 0.01 ? a cs = v dd dynamic specifications (note 1) cs low to valid amplifier output, turn on time t on ?410scs low 0.2 v dd , g = +1 v/v, v in = v dd /2, v out = 0.9 v dd /2, v dd = 5.0v cs high to amplifier output high-z t off ?0.01? scs high 0.8 v dd , g = +1 v/v, v in = v dd /2, v out = 0.1 v dd /2 hysteresis v hyst ?0.6? vv dd = 5v note 1: the input condition (v in ) specified applies to both op amp a and b of the mcp6275. the dynamic specification is tested at the output of op amp b (v outb ). v il high-z t on v ih cs t off v out -0.7 a (typ.) high-z i ss i cs 0.7 a (typ.) 0.7 a (typ.) -0.7 a (typ.) -170 a (typ.) 10 na (typ.)
? 2006 microchip technology inc. ds21810e-page 5 mcp6271/1r/2/3/4/5 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = +2.0v to +5.5v, v ss =gnd, v cm =v dd /2, v out v dd /2, r l =10k to v dd /2, c l = 60 pf and cs is tied low. figure 2-1: input offset voltage. figure 2-2: input bias current at t a =+85c. figure 2-3: input offset voltage vs. common mode input voltage, with v dd =2.0v. figure 2-4: input offset voltage drift. figure 2-5: input bias current at t a = +125c. figure 2-6: input offset voltage vs. common mode input voltage, with v dd =5.5v. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purpose s only. the performance characteristics listed herein are not tested or guaranteed. in so me graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power suppl y range) and therefore outs ide the warranted range. 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% -3.0 -2.4 -1.8 -1.2 -0.6 0.0 0.6 1.2 1.8 2.4 3.0 input offset voltage (mv) percentage of occurrences 832 samples v cm = v ss 0% 4% 8% 12% 16% 20% 24% 28% 32% 0 102030405060708090100 input bias current (pa) percentage of occurrences 422 samples t a = 85c -100 -50 0 50 100 150 200 250 300 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 common mode input voltage (v) input offset voltage (v) v dd = 2.0v t a = +125c t a = +85c t a = +25c t a = -40c 0% 2% 4% 6% 8% 10% 12% 14% -10 -8 -6 -4 -2 0 2 4 6 8 10 input offset voltage drift (v/c) percentage of occurrences 832 samples v cm = v ss t a = -40c to +125c 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 22% 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 input bias current (na) percentage of occurrences 422 samples t a = +125c -100 -50 0 50 100 150 200 250 300 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) input offset voltage (v) v dd = 5.5v t a = +85c t a = +25c t a = -40c t a = +125c
mcp6271/1r/2/3/4/5 ds21810e-page 6 ? 2006 microchip technology inc. typical performance curves (continued) note: unless otherwise indicated, t a = +25c, v cm = +2.0v to +5.5v, v ss = gnd, v cm =v dd /2, v out v dd /2, r l =10k to v dd /2, c l = 60 pf, and cs is tied low. figure 2-7: common mode input voltage range lower limit vs. temperature. figure 2-8: input offset voltage vs. output voltage. figure 2-9: cmrr, psrr vs. frequency. figure 2-10: common mode input voltage range upper limit vs. temperature. figure 2-11: input bias, input offset currents vs. temperature. figure 2-12: cmrr, psrr vs. temperature. -0.50 -0.45 -0.40 -0.35 -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 -50 -25 0 25 50 75 100 125 ambient temperature (c) common mode input voltage range limit (v) typical lower (v cm ? v ss ) limit v dd = 5.5v v dd = 2.0v -100 -50 0 50 100 150 200 250 300 0.00.51.01.52.02.53.03.54.04.55.05.5 output voltage (v) input offset voltage (v) v dd = 2.0v v cm = v ss representative part v dd = 5.5v 20 30 40 50 60 70 80 90 100 110 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) cmrr, psrr (db) 1 10k 100k 1m 100 10 1k psrr? psrr+ cmrr 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 -50-25 0 255075100125 ambient temperature (c) common mode input voltage range limit (v) typical upper (v cm ? v dd ) limit v dd = 5.5 v v dd = 2.0v 1 10 100 1,000 10,000 45 55 65 75 85 95 105 115 125 ambient temperature (c) input bias, offset currents (pa) input bias current v cm = v dd v dd = 5.5v input offset current 60 70 80 90 100 110 120 -50 -25 0 25 50 75 100 125 ambient temperature (c) psrr, cmrr (db) psrr (v cm = v ss ) cmrr
? 2006 microchip technology inc. ds21810e-page 7 mcp6271/1r/2/3/4/5 typical performance curves (continued) note: unless otherwise indicated, t a = +25c, v cm = +2.0v to +5.5v, v ss = gnd, v cm =v dd /2, v out v dd /2, r l =10k to v dd /2, c l = 60 pf, and cs is tied low. figure 2-13: input bias, offs et currents vs. common mode input voltage, with t a =+85c. figure 2-14: quiescent current vs. supply voltage. figure 2-15: open-loop gain, phase vs. frequency. figure 2-16: input bias, offset currents vs. common mode input voltage, with t a = +125c. figure 2-17: output voltage headroom vs. output current magnitude. figure 2-18: gain bandwidth product, phase margin vs. temperature. -25 -15 -5 5 15 25 35 45 55 0.00.51.01.52.02.53.03.54.04.55.05.5 common mode input voltage (v) input bias, offset currents (pa) t a = 85c v dd = 5.5v input bias current input offset current 0 50 100 150 200 250 0.00.51.01.52.02.53.03.54.04.55.05.5 power supply voltage (v) quiescent current (a/amplifier) t a = +125c t a = +85c t a = +25c t a = -40c -20 0 20 40 60 80 100 120 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 frequency (hz) open-loop gain (db) -210 -180 -150 -120 -90 -60 -30 0 open-loop phase () gain phase 0.1 1 10 100 1k 10k 100k 1m 10m 100m -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage (v) input bias, offset currents (na) t a = 125c v dd = 5.5v input bias current input offset current 1 10 100 1000 0.01 0.1 1 10 output current magnitude (ma) ouput voltage headroom (mv) v ol ? v ss v dd ? v oh 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -50 -25 0 25 50 75 100 125 ambient temperature (c) gain bandwidth product (mhz) 50 55 60 65 70 75 80 phase margin () pm, v dd = 5.5 v v dd = 2.0 v gbwp, v dd = 5.5 v v dd = 2.0 v
mcp6271/1r/2/3/4/5 ds21810e-page 8 ? 2006 microchip technology inc. typical performance curves (continued) note: unless otherwise indicated, t a = +25c, v cm = +2.0v to +5.5v, v ss = gnd, v cm =v dd /2, v out v dd /2, r l =10k to v dd /2, c l = 60 pf, and cs is tied low. figure 2-19: maximum output voltage swing vs. frequency. figure 2-20: input noise voltage density vs. frequency. figure 2-21: output short circuit current vs. supply voltage. figure 2-22: slew rate vs. temperature. figure 2-23: input noise voltage density vs. common mode input voltage, with f = 1 khz. figure 2-24: channel-to-channel separation vs. frequency (MCP6272 and mcp6274). 0.1 1 10 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 frequency (hz) maximum output voltage swing (v p-p ) v dd = 2.0v 1k 10k 100k 1m v dd = 5.5v 10m 10 100 1,000 1.e- 01 1.e+ 00 1.e+ 01 1.e+ 02 1.e+ 03 1.e+ 04 1.e+ 05 1.e+ 06 frequency (hz) input noise voltage density (nv/ ? hz) 0.1 100 10 1k 100k 10k 1m 1 0 5 10 15 20 25 30 35 0.00.51.01.52.02.53.03.54.04.55.05.5 power supply voltage (v) ouptut short-circuit current (ma) t a = +125c t a = +85c t a = +25c t a = -40c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -50 -25 0 25 50 75 100 125 ambient temperature (c) slew rate (v/s) falling edge v dd = 5.5v v dd = 2.0v rising edge 0 5 10 15 20 25 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage (v) input noise voltage density (nv/ hz) f = 1 khz v dd = 5.0v 100 110 120 130 140 1 10 100 frequency (khz) channel-to-channel separation (db)
? 2006 microchip technology inc. ds21810e-page 9 mcp6271/1r/2/3/4/5 typical performance curves (continued) note: unless otherwise indicated, t a = +25c, v cm = +2.0v to +5.5v, v ss = gnd, v cm =v dd /2, v out v dd /2, r l =10k to v dd /2, c l = 60 pf, and cs is tied low. figure 2-25: quiescent current vs. chip select (cs ) voltage, with v dd = 2.0v (mcp6273 and mcp6275 only). figure 2-26: large signal non-inverting pulse response. figure 2-27: small signal non-inverting pulse response. figure 2-28: quiescent current vs. chip select (cs ) voltage, with v dd = 5.5v (mcp6273 and mcp6275 only). figure 2-29: large signal inverting pulse response. figure 2-30: small signal inverting pulse response. 0 50 100 150 200 250 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 chip select voltage (v) quiescent current (a/amplifier) hysteresis op amp turns off op amp turns on v dd = 2.0v cs swept high-to-low cs swept low-to-high 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time (5 s/div) output voltage (v) g = +1 v/v v dd = 5.0v time (2 s/div) output voltage (10 mv/div) g = +1 v/v 0 100 200 300 400 500 600 700 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 chip select voltage (v) quiescent current (a/amplifier) hysteresis op amp turns on/off cs swept low-to-high cs swept high-to-low v dd = 5.5v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time (5 s/div) output voltage (v) g = -1 v/v v dd = 5.0v time (2 s/div) output voltage (10 mv/div) g = -1 v/v
mcp6271/1r/2/3/4/5 ds21810e-page 10 ? 2006 microchip technology inc. typical performance curves (continued) note: unless otherwise indicated, t a = +25c, v cm = +2.0v to +5.5v, v ss = gnd, v cm =v dd /2, v out v dd /2, r l =10k to v dd /2, c l = 60 pf, and cs is tied low. figure 2-31: chip select (cs ) to amplifier output re sponse time, with v dd = 2.0v (mcp6273 and mcp6275 only). figure 2-32: input current vs. input voltage. figure 2-33: chip select (cs ) to amplifier output response time, with v dd = 5,5v (mcp6273 and mcp6275 only). figure 2-34: the mcp6271/1r/2/3/4/5 show no phase reversal. 0.0 0.5 1.0 1.5 2.0 2.5 time (5 s/div) chip select, output voltages (v) v out output on output high-z v dd = 2.0v g = +1 v/v v in = v ss cs 1.e-12 1.e-11 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 1.e-05 1.e-04 1.e-03 1.e-02 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 input voltage (v) input current magnitude (a) +125c +85c +25c -40c 10m 1m 100 10 1 100n 10n 1n 100p 10p 1p 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 time (5 s/div) chip select, output voltages (v) v out output on output high-z v dd = 5.5v g = +1 v/v v in = v ss cs -1 0 1 2 3 4 5 6 time (1 ms/div) input, output voltage (v) v dd = 5.0v g = +2 v/v v in v out
? 2006 microchip technology inc. ds21810e-page 11 mcp6271/1r/2/3/4/5 3.0 pin descriptions descriptions of the pins are listed in table 3-1 (single op amps) and table 3-2 (dual and quad op amps). table 3-1: pin function table for single op amps table 3-2: pin function table for dual and quad op amps 3.1 analog outputs the output pins are low impedance voltage sources. 3.2 analog inputs the non-inverting and inverting inputs are high impedance cmos inputs with low bias currents. 3.3 mcp6275?s v outa /v inb + pin for the mcp6275 only, the output of op amp a is connected directly to the non- inverting input of op amp b; this is the v outa /v inb + pin. this connection makes it possible to provide a cs pin for duals in 8-pin packages. 3.4 cs digital input this is a cmos, schmitt triggered input that places the part into a low power mode of operation. 3.5 power supply (v ss and v dd ) the positive power supply (v dd ) is 2.0v to 5.5v higher than the negative power supply (v ss ). for normal operation, the other pins are between v ss and v dd . typically, these parts are used in a single (positive) supply configuration. in this case, v ss is connected to ground and v dd is connected to the supply. v dd will need a local bypass capacitor (typically 0.01 f to 0.1 f) within 2 mm of the v dd pin. these parts need to use a bulk capacitor (within 100 mm), which can be shared with nearby analog parts. mcp6271 (pdip, soic, msop) mcp6271 (sot-23-5) mcp6271r (sot-23-5) mcp6273 (pdip, soic, msop) mcp6273 (sot-23-6) symbol description 244 24v in ? inverting input 333 33v in + non-inverting input 425 42v ss negative power supply 611 61v out analog output 752 76v dd positive power supply ??? 8 5cs chip select 1,5,8 ? ? 1,5 ? nc no internal connection MCP6272 mcp6274 mcp6275 symbol description 11?v outa analog output (op amp a) 222 v ina ? inverting input (op amp a) 333 v ina + non-inverting input (op amp a) 848 v dd positive power supply 55?v inb + non-inverting input (op amp b) 666 v inb ? inverting input (op amp b) 777v outb analog output (op amp b) ?8?v outc analog output (op amp c) ?9? v inc ? inverting input (op amp c) ?10? v inc + non-inverting input (op amp c) 4114 v ss negative power supply ?12? v ind + non-inverting input (op amp d) ?13? v ind ? inverting input (op amp d) ?14? v outd analog output (op amp d) ?? 1v outa /v inb + analog output (op amp a)/non-inverting input (op amp b) ?? 5 cs chip select
mcp6271/1r/2/3/4/5 ds21810e-page 12 ? 2006 microchip technology inc. 4.0 application information the mcp6271/1r/2/3/4/5 family of op amps is manufactured using microchi p?s state of the art cmos process, specifically designed for low cost, low power and general purpose applications. the low supply voltage, low quiescent current and wide bandwidth make the mcp6271/1r/2/3/4/5 ideal for battery powered applications. 4.1 rail-to-rail inputs the input stage of the mcp6271/1r/2/3/4/5 op amps uses two differential cmos input stages in parallel. one operates at low common mode input voltage (v cm , which is aproximately equal to v in + and v in ? in normal operation) and the other at high v cm . with this topol- ogy, the input operates with v cm up to 0.3v past either supply rail (see figure 2-7 and figure 2-10 ). the input offset voltage (v os ) is measured at v cm =v ss ?0.3v and v dd + 0.3v to ensure proper operation. the transition between the two input stage occurs when v cm v dd ? 1.1v (see figure 2-3 and figure 2- 6 ). for the best distortion and gain linearity, with non- inverting gains, avoid this region of operation. 4.1.1 phase reversal the input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. figure 2-34 shows an input voltage exceeding both supplies with no phase inversion. 4.1.2 input voltage and current limits the esd protection on the inputs can be depicted as shown in figure 4-1 . this structure was chosen to protect the input transistors, and to minimize input bias current (i b ). the input esd diodes clamp the inputs when they try to go more than one diode drop below v ss . they also clamp any voltages that go too far above v dd ; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick esd events within the specified limits. figure 4-1: simplified analog input esd structures. in order to prevent damag e and/or improper operation of these amplifiers, the circuit must limit the currents (and voltages) at t he input pins (see absolute maxi- mum ratings ? at the beginning of section 1.0 ?elec- trical characteristics? ). figure 4-2 shows the recommended approach to protecting these inputs. the internal esd diodes prevent the input pins (v in + and v in ?) from going too far below ground, and the resistors r 1 and r 2 limit the possible current drawn out of the input pins. diodes d 1 and d 2 prevent the input pins (v in + and v in ?) from going too far above v dd , and dump any currents onto v dd . when implemented as shown, resistors r 1 and r 2 also limit the current through d 1 and d 2 . figure 4-2: protecting the analog inputs. it is also possible to connect the diodes to the left of the resistor r 1 and r 2 . in this case, the currents through the diodes d 1 and d 2 need to be limited by some other mechanism. the resistors th en serve as in-rush current limiters; the dc current into the input pins (v in + and v in ?) should be very small. a significant amount of current can flow out of the inputs (through the esd diodes) when the common mode voltage (v cm ) is below ground (v ss ); see figure 2-32 . applications that are high impedance may need to limit the useable voltage range. 4.2 rail-to-rail output the output voltage range of the mcp6271/1r/2/3/4/5 op amps is v dd ?15mv (min.) and v ss +15mv (max.) when r l =10k is connected to v dd /2 and v dd = 5.5v. refer to figure 2-17 for more information. bond pad bond pad bond pad v dd v in + v ss input stage bond pad v in ? v 1 mcp627x r 1 v dd d 1 r 1 > v ss ? (minimum expected v 1 ) 2ma v out r 2 > v ss ? (minimum expected v 2 ) 2ma v 2 r 2 d 2
? 2006 microchip technology inc. ds21810e-page 13 mcp6271/1r/2/3/4/5 4.3 capacitive loads driving large capacitive loads can cause stability problems for voltage feedback op amps. as the load capacitance increases, the feedback loop?s phase margin decreases and the closed-loop bandwidth is reduced. this produces gain peaking in the frequency response, with overshoot and ringing in the step response. a unity gain buffer (g = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. when driving large capacitive loads with these op amps (e.g., > 100 pf when g = +1), a small series resistor at the output (r iso in figure 4-3 ) improves the feedback loop?s phase margin (stability) by making the output load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 4-3: output resistor, r iso stabilizes large capacitive loads. figure 4-4 gives recommended r iso values for different capacitive loads and gains. the x-axis is the normalized load capacitance (c l /g n ), where g n is the circuit's noise gain. for non-inverting gains, g n and the signal gain are equal. for inverting gains, g n is 1+|signal gain| (e.g., ?1 v/v gives g n = +2 v/v). figure 4-4: recommended r iso values for capacitive loads. after selecting r iso for your circuit, double check the resulting frequency response peaking and step response overshoot. modify r iso 's value until the response is reasonable. bench evaluation and simulations with the mcp6271/1r/2/3/4/5 spice macro model are helpful. 4.4 mcp6273/5 chip select (cs ) the mcp6273 and mcp6275 are single and dual op amps with chip select (cs ), respectively. when cs is pulled high, the supply current drops to 0.7 a (typ.) and flows through the cs pin to v ss . when this happens, the amplifier output is put into a high impedance state. by pulling cs low, the amplifier is enabled. the cs pin has a 5 m (typ.) pull-down resistor connected to v ss , so it will go low if the cs pin is left floating. figure 1-1 shows the output voltage and supply current response to a cs pulse. 4.5 cascaded dual op amps (mcp6275) the mcp6275 is a dual op amp with chip select (cs ). the chip select input is available on what would be the non-inverting input of a standard dual op amp (pin 5). this pin is available because the output of op amp a connects to the non-inverting input of op amp b, as shown in figure 4-5 . the chip select input, which can be connected to a microcontroller i/o line, puts the device in low power mode. refer to section 4.4 ?mcp6273/5 chip select (cs )? . figure 4-5: cascaded gain amplifier. the output of op amp a is loaded by the input impedance of op amp b, which is typically 10 13 ?? 6 pf, as specified in t he dc specification table (refer to section 4.3 ?capacitive loads? for further details regarding capacitive loads). the common mode input range of these op amps is specified in the data sheet as v ss ? 300 mv and v dd + 300 mv. however, since the output of op amp a is limited to v ol and v oh (20 mv from the rails with a 10 k load), the non-inverting input range of op amp b is limited to the common mode input range of v ss + 20 mv and v dd ?20mv. v in r iso v out c l ? + mcp627x 10 100 1,000 10 100 1,000 10,000 normalized load capacitance; c l / g n (pf) recommended r iso ( : ) g n = 1 v/v g n = 2 v/v g n t 4 v/v a b cs 2 3 5 6 7 v ina + v outb mcp6275 1 v ina ? v outa /v inb + v inb ?
mcp6271/1r/2/3/4/5 ds21810e-page 14 ? 2006 microchip technology inc. 4.6 unused amplifiers an unused op amp in a quad package (mcp6274) should be configured as shown in figure 4-6 . these circuits prevent the output from toggling and causing crosstalk. in circuit a, r 1 and r 2 produce a voltage within its output voltage range (v oh , v ol ). the op amp buffers this voltage, which can be used elsewhere in the circuit. circuit b uses the minimum number of components and operates as a comparator. figure 4-6: unused op amps. 4.7 supply bypass with this family of operat ional amplifiers, the power supply pin (v dd for single supply) should have a local bypass capacitor (i.e., 0.01 f to 0.1 f) within 2 mm for good, high frequency performance. it also needs a bulk capacitor (i.e., 1 f or larger) within 100 mm to provide large, slow currents. this bulk capacitor can be shared with nearby analog parts. 4.8 pcb surface leakage in applications where low input bias current is critical, printed circuit board (pcb) surface leakage effects need to be considered. surface leakage is caused by humidity, dust or other contamination on the board. under low humidity conditions, a typical resistance between nearby traces is 10 12 . a 5v difference would cause 5 pa of current to flow . this is greater than the mcp6271/1r/2/3/4/5 family?s bias current at 25c (1 pa, typ.). the easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). the guard ring is biased at the same voltage as the sensitive pin. an example of this type of layout is illustrated in figure 4-7 . figure 4-7: example guard ring layout for inverting gain. 1. for inverting gain and transimpedance amplifiers (convert current to voltage, such as photo detectors): a) connect the guard ring to the non-inverting input pin (v in +). this biases the guard ring to the same reference voltage as the op amp (e.g., v dd /2 or ground). b) connect the inverting pin (v in ?) to the input with a wire that does not touch the pcb surface. 2. non-inverting gain and unity gain buffer: a) connect the non-inverting pin (v in +) to the input with a wire that does not touch the pcb surface. b) connect the guard ring to the inverting input pin (v in ?). this biases the guard ring to the common mode input voltage. ? mcp6274 (a) v dd ? mcp6274 (b) r 1 r 2 v dd v dd guard ring v ss v in ?v in +
? 2006 microchip technology inc. ds21810e-page 15 mcp6271/1r/2/3/4/5 4.9 application circuits 4.9.1 active full-wave rectifier the mcp6271/1r/2/3/4/5 family of amplifiers can be used in applications such as an active full-wave rectifier or an absolute value circuit, as shown in figure 4-8 . the amplifier and feedback loops in this active voltage rectifier circuit eliminate the diode drop problem that exists in a passive voltage rectifier. this circuit behaves as a follower (the output follows the input) as long as the input signal is more positive than the reference voltage. if the input signal is more negative than the reference voltage, however, the circuit behaves as an inverting amplifier. therefore, the output voltage will always be above the reference voltage, regardless of the input signal. figure 4-8: active full-wave rectifier. the design equations give a gain of 1 from v in to v out , and produce rail-to-rail outputs. 4.9.2 lossy non-inverting integrator the non-inverting integrator shown in figure 4-9 is easy to build. it saves one op amp over the typical miller integrator plus inve rting amplifier configuration. the phase accuracy of this integrator depends on the matching of the input and feedback resistor-capacitor time constants. r f makes this a lossy integrator (it has finite gain at dc), and makes this integrator stable by itself. figure 4-9: non-inverting integrator. ? + ? + v in v out v ref v ref r 1 r 3 r 4 r 5 r 2 op amp a op amp b d 1 d 2 v ref v ref time time input output r 5 r 2 r 4 2 r 3 ------------ = r 1 r 2 r 3 == 1/2 MCP6272 1/2 MCP6272 r 4 r 3 <1 v d 1 v ref v ss ? --------------------------- - ? ?? ?? + _ c 1 c 2 r 1 r 2 v in v out r f v out v in ------------- 1 sr 1 c 1 () -------------------- f 1 2 r 1 c 1 1 r f r 2 ? + () --------------------------------------------------- , mcp6271 r f r 2 r 1 c 1 r 2 || r f () c 2 = c 2
mcp6271/1r/2/3/4/5 ds21810e-page 16 ? 2006 microchip technology inc. 4.9.3 cascaded op amp applications the mcp6275 provides the flexibility of low power mode for dual op amps in an 8-pin package. the mcp6275 eliminates the added cost and space in a battery powered application by using two single op amps with chip select (cs ) lines or a 10-pin device with one cs line for both op amps. since the two op amps are internally casc aded, this device cannot be used in circuits that require active or passive elements between the two op amps. however, there are several applications where this op amp configuration with a cs line becomes suitable. the circuits below show possible applications for this device. 4.9.3.1 load isolation with the cascaded op amp configuration, op amp b can be used to isolate the load from op amp a. in applications where op amp a is driving capacitive or low resistive loads in the feedback loop (such as an integrator or filter circuit) the op amp may not have sufficient source current to drive the load. in this case, op amp b can be used as a buffer. figure 4-10: isolating the load with a buffer. 4.9.3.2 cascaded gain figure 4-11 shows a cascaded gain circuit configura- tion with chip select. op amps a and b are configured in a non-inverting amplifie r configuration. in this configuration, it is important to note that the input offset voltage of op amp a is amplified by the gain of op amp a and b, as shown below: therefore, it is recommended that you set most of the gain with op amp a and use op amp b with relatively small gain (e.g., a unity gain buffer). figure 4-11: cascaded gain circuit configuration. 4.9.3.3 difference amplifier figure 4-12 shows op amp a configured as a difference amplifier with chip select. in this configuration, it is recommended that well matched resistors (e.g., 0.1%) be used to increase the common mode rejection ratio (cmrr). op amp b can be used to provide additional gain and isolate the load fr om the difference amplifier. figure 4-12: difference amp lifier circuit. 4.9.3.4 inverting int egrator with active compensation and chip select figure 4-13 uses an active compensator (op amp b) to compensate for the non-ideal op amp characteristics introduced at higher frequencies. this circuit uses op amp b as a unity gain buffer to isolate the integration capacitor c 1 from op amp a and drives the capacitor with a low impedance source. since both op amps are matched very well, they provide a high quality integrator. figure 4-13: integrator circuit with active compensation. a cs v outb mcp6275 b load v out v in g a g b v osa g a g b v osb g b + + = where: g a = op amp a gain g b = op amp b gain v osa = op amp a input offset voltage v osb = op amp b input offset voltage a cs r 4 r 3 r 2 r 1 v in v out mcp6275 b a cs r 2 r 1 r 4 r 3 v out mcp6275 v in2 b r 2 r 1 v in1 a cs r 1 c 1 v out mcp6275 v in b
? 2006 microchip technology inc. ds21810e-page 17 mcp6271/1r/2/3/4/5 4.9.3.5 second order mfb with an extra pole-zero pair figure 4-14 is a second order multiple feedback low- pass filter with chip select. use the filterlab ? software from microchip technology inc. to determine the r and c values for op amp a?s second order filter. op amp b can be used to add a pole-zero pair using c 3 , r 6 and r 7 . figure 4-14: second order multiple feedback low-pass filter with an extra pole- zero pair. 4.9.3.6 second order sallen-key with an extra pole-zero pair figure 4-15 is a second order sallen-key low-pass filter with chip sele ct. use the filterlab ? software from microchip to determine the r and c values for op amp a?s second order filter. op amp b can be used to add a pole-zero pair using c 3 , r 5 and r 6 . figure 4-15: second order sallen-key low-pass filter wit h an extra pole-zero pair and chip select. 4.9.3.7 capacitorless second order low-pass filter with chip select the low-pass filter shown in figure 4-16 does not require external capacitors and uses only three external resistors; the op amp?s gbwp sets the corner frequency. r 1 and r 2 are used to set the circuit gain. r 3 is used to set the q. to avoid gain peaking in the frequency response, q needs to be low (lower values need to be selected for r 3 ). note that the amplifier bandwidth varies greatly over temperature and process. this configuration, however, provides a low cost solution for applications with high bandwidth requirements. figure 4-16: capacitorless second order low-pass filter wit h chip select. a cs r 1 r 6 c 3 v out mcp6275 b r 5 r 4 v dd r 7 c 1 r 3 r 2 v in a cs r 5 c 3 v out mcp6275 b r 6 r 4 r 3 v in r 2 r 1 c 1 c 2 a cs r 3 r 2 v out mcp6275 b v ref r 1 v in
mcp6271/1r/2/3/4/5 ds21810e-page 18 ? 2006 microchip technology inc. 5.0 design tools microchip provides the basic design tools needed for the mcp6271/1r/2/3/4/5 family of op amps. 5.1 spice macro model the latest spice macro model for the mcp6271/1r/2/3/4/5 op amps is available on our web site at www.microchip.com. this model is intended to be an initial design tool that works well in the op amp?s linear region of operation at room temperature. see the macro model file for information on its capabilities. bench testing is a very important part of any design and cannot be replaced with simulations. also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 filterlab ? software microchip?s filterlab software is an innovative tool that simplifies analog active filter (using op amps) design. it is available free of char ge from our web site at www.microchip.com. the filterlab software tool provides full schematic diagram s of the filter circuit with component values. it also outputs the filter circuit in spice format, which can be used with the macro model to simulate actual filter performance.
? 2006 microchip technology inc. ds21810e-page 19 mcp6271/1r/2/3/4/5 6.0 packaging information 6.1 package marking information xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (150 mil) example: xxxxxxxx xxxxyyww nnn 8-lead msop example: xxxxxx ywwnnn 6271 e 644256 5-lead sot-23 ( mcp6271 and mcp6271r ) example: xxnn cg25 device code mcp6271 cgnn mcp6271r etnn note: applies to 5-lead sot-23 6-lead sot-23 ( mcp6273 ) example: xxnn ck25 mcp6271 e/p^^256 0644 mcp6271 e/p256 0437 or mcp6271 e/sn0437 256 mcp6271 e sn^^0644 256 or legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3 e 3 e
mcp6271/1r/2/3/4/5 ds21810e-page 20 ? 2006 microchip technology inc. package marking information (continued) 14-lead pdip (300 mil) (mcp6274) example: 14-lead tssop (mcp6274) example: 14-lead soic (150 mil) (mcp6274) example: xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn xxxxxxxxxx yywwnnn xxxxxx yyww nnn mcp6274 -e/p 0437256 6274 est 0437 256 xxxxxxxxxx mcp6274 esl 0437256 mcp6274 0644256 mcp6274 0644256 or e/p^^ or e/sl^^ 3 e 3 e
? 2006 microchip technology inc. ds21810e-page 21 mcp6271/1r/2/3/4/5 5-lead plastic small outline transistor (ot) (sot-23) note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging 1 p d b n e e1 l c a2 a a1 p1 10 5 0 10 5 0 b mold draft angle bottom 10 5 0 10 5 0 a mold draft angle top 0.50 0.43 0.35 .020 .017 .014 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 10 5 0 10 5 0 f foot angle 0.55 0.45 0.35 .022 .018 .014 l foot length 3.10 2.95 2.80 .122 .116 .110 d overall length 1.75 1.63 1.50 .069 .064 .059 e1 molded package width 3.00 2.80 2.60 .118 .110 .102 e overall width 0.15 0.08 0.00 .006 .003 .000 a1 standoff 1.30 1.10 0.90 .051 .043 .035 a2 molded package thickness 1.45 1.18 0.90 .057 .046 .035 a overall height 1.90 .075 p1 outside lead pitch (basic) 0.95 .038 p pitch 5 5 n number of pins max nom min max nom min dimension limits millimeters inches * units dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005" (0.127mm) per s ide. notes: eiaj equivalent: sc-74a drawing no. c04-091 * controlling parameter revised 09-12-05
mcp6271/1r/2/3/4/5 ds21810e-page 22 ? 2006 microchip technology inc. 6-lead plastic small outline transistor (ch) (sot-23) note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging 1 d b n e e1 l c a2 a a1 p1 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.50 0.43 0.35 .020 .017 .014 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 10 5 0 10 5 0 foot angle 0.55 0.45 0.35 .022 .018 .014 l foot length 3.10 2.95 2.80 .122 .116 .110 d overall length 1.75 1.63 1.50 .069 .064 .059 e1 molded package width 3.00 2.80 2.60 .118 .110 .102 e overall width 0.15 0.08 0.00 .006 .003 .000 a1 standoff 1.30 1.10 0.90 .051 .043 .035 a2 molded package thickness 1.45 1.18 0.90 .057 .046 .035 a overall height 1.90 bsc .075 bsc p1 outside lead pitch 0.95 bsc .038 bsc p pitch 6 6 n number of pins max nom min max nom min dimension limits millimeters inches * units dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005" (0.127mm) per s ide. notes: jeita (formerly eiaj) equivalent: sc-74a * controlling parameter drawing no. c04-120 bsc: basic dimension. theoretically exact value shown without tolerances. see asme y14.5m revised 09-12-05
? 2006 microchip technology inc. ds21810e-page 23 mcp6271/1r/2/3/4/5 8-lead plastic micro small outline package (ms) (msop) note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging l l1 ? c a2 a1 a b 2 1 note 1 e e e1 d n numb e r of pins pitch ov e rall h e ight mold e d packag e thickn e ss standoff ov e rall width mold e d packag e width ov e rall l e ngth foot l e ngth footprint foot angl e l e ad thickn e ss l e ad width units dim e nsion limits n e a a2 a1 e e1 d l l1 ? c b ? 0.75 0.00 0.40 0 0.08 0.22 8 0.65 bsc ? 0.85 ? 4.90 bsc 3 .00 bsc 3 .00 bsc 0.60 0.95 ref ? ? ? 1.10 0.95 0.15 0.80 8 0.2 3 0.40 min nom max millimeters notes: 1. pin 1 visual ind e x f e atur e may vary, but must b e locat e d within th e hatch e d ar e a. 2. dim e nsions d and e1 do not includ e mold flash or protrusions. mold flash or protrusions shall not e xc ee d 0.15 mm p e r sid e . 3 . dim e nsioning and tol e rancing p e r asme y14.5m bsc: basic dim e nsion. th e or e tically e xact valu e shown without tol e ranc e s. ref: r e f e r e nc e dim e nsion, usually without tol e ranc e , for information purpos e s only. microchip t e chnology drawing no. c04?111, s e pt. 8, 2006
mcp6271/1r/2/3/4/5 ds21810e-page 24 ? 2006 microchip technology inc. 8-lead plastic dual in-line (p) ? 300 mil (pdip) note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or prot rusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
? 2006 microchip technology inc. ds21810e-page 25 mcp6271/1r/2/3/4/5 8-lead plastic small outline (sn) ? narrow, 150 mil (soic) note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or prot rusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
mcp6271/1r/2/3/4/5 ds21810e-page 26 ? 2006 microchip technology inc. 14-lead plastic dual in-line (p) ? 300 mil (pdip) note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging e1 n d 1 2 eb e c a a1 b b1 l a2 p units inches* millimeters dimension limits min nom max min nom max number of pins n 14 14 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .740 .750 .760 18.80 19.05 19.30 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 5 10 15 5 10 15 5 10 15 5 10 15 mold draft angle bottom * controlling parameter notes: dimensions d and e1 do not include mold flash or prot rusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-005 significant characteristic
? 2006 microchip technology inc. ds21810e-page 27 mcp6271/1r/2/3/4/5 14-lead plastic small outline (sl) ? narrow, 150 mil (soic) note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 8.81 8.69 8.56 .347 .342 .337 d overall length 3.99 3.90 3.81 .157 .154 .150 e1 molded package width 6.20 5.99 5.79 .244 .236 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters inches * units 2 1 d p n b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per si de. jedec equivalent: ms-012 drawing no. c04-065 revised 7-20-06 significant characteristic
mcp6271/1r/2/3/4/5 ds21810e-page 28 ? 2006 microchip technology inc. 14-lead plastic thin shrink small outline (st) ? 4.4 mm (tssop) note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging l c 2 1 d n b p e1 e a2 a1 a 8 4 0 8 4 0 foot angle mold draft angle bottom 12 ref mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 5.10 5.00 4.90 .201 .197 .193 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 1.05 1.00 .043 .041 .039 a overall height 0.65 bsc .026 bsc p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters * inches units dimensions d and e1 do not include mold fla sh or protrusions. mold flash or protrusions shall not exceed .005" (0.127mm) per s ide. notes: jedec equivalent: mo-153 ab-1 revised: 08-17-05 * controlling parameter bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tole rance, for information purposes only. see asme y14.5m see asme y14.5m drawing no. c04-087 12 ref 12 ref 12 ref
? 2006 microchip technology inc. ds21810e-page 29 mcp6271/1r/2/3/4/5 appendix a: revision history revision e (december 2006) the following is the list of modifications: 1. updated specifications ( section 1.0 ?electrical characteristics? ): a) clarified absolute maximum analog input voltage and current specifications. b) clarified v cmr , v ol , v oh , and pm specifications. c) corrected the typical e ni . 2. added plots on common mode input range behavior vs. temperature and supply voltage ( section 2.0 ?typical performance curves? ). 3. added applications writeup on unused op amps and corrected description of floating cs pin behavior ( section 4.0 ?application informa- tion? ). 4. updated package information ( section 6.0 ?packaging information? ): a) corrected package markings. b) added disclaimer to package outline drawings. revision d (december 2004) the following is the list of modifications: 1. added sot-23-5 packages for the dstemp and mcp6271r single op amps. 2. added sot-23-6 packages for the dstemp single op amp. 3. added section 3.0 ?pin descriptions? . 4. corrected application circuits ( section 4.9 ?application circuits? ). 5. added sot-23-5 and sot-23-6 packages and corrected package marking information ( section 6.0 ?packaging information? ). 6. added appendix a: revision history. revision c (june 2004) revision b (october 2003) revision a (june 2003) ? original data sheet release.
mcp6271/1r/2/3/4/5 ds21810e-page 30 ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. ds21810e-page 31 mcp6271/1r/2/3/4/5 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: mcp6271: single op amp mcp6271t: single op amp (tape and reel) (soic, msop, sot-23-5) mcp6271rt: single op amp (tape and reel) (sot-23-5) MCP6272: dual op amp MCP6272t: dual op amp (tape and reel) (soic, msop) mcp6273: single op amp with chip select mcp6273t: single op amp with chip select (tape and reel) (soic, msop, sot-23-6) mcp6274: quad op amp mcp6274t: quad op amp (tape and reel) (soic, tssop) mcp6275: dual op amp with chip select mcp6275t: dual op amp with chip select (tape and reel) (soic, msop) temperature range: e = -40c to +125c package: ot = plastic small outline transistor (sot-23), 5-lead (mcp6271, mcp6271r) ch = plastic small outline transistor (sot-23), 6-lead (mcp6273) ms = plastic msop, 8-lead p = plastic dip (300 mil body), 8-lead, 14-lead sn = plastic soic, (150 mil body), 8-lead sl = plastic soic (150 mil body), 14-lead st = plastic tssop (4.4 mm body), 14-lead part no. x /xx package temperature range device examples: a) mcp6271-e/sn: extended temperature, 8ld soic package. b) mcp6271-e/ms: extended temperature, 8ld msop package. c) mcp6271-e/p: extended temperature, 8ld pdip package. d) mcp6271t-e/ot: tape and reel, extended temperature, 5ld sot-23 package. a) mcp6271rt-e/ot: tape and reel, extended temperature, 5ld sot-23 package. a) MCP6272-e/sn: extended temperature, 8ld soic package. b) MCP6272-e/ms: extended temperature, 8ld msop package. c) MCP6272-e/p: extended temperature, 8ld pdip package. d) MCP6272t-e/sn: tape and reel, extended temperature, 8ld soic package. a) mcp6273-e/sn: extended temperature, 8ld soic package. b) mcp6273-e/ms: extended temperature, 8ld msop package. c) mcp6273-e/p: extended temperature, 8ld pdip package. d) mcp6273t-e/ch: extended temperature, 6ld sot-23 package. a) mcp6274-e/p: extended temperature, 14ld pdip package. b) mcp6274t-e/sl: tape and reel, extended temperature, 14ld soic package. c) mcp6274-e/sl: extended temperature, 14ld soic package. d) mcp6274-e/st: extended temperature, 14ld tssop package. a) mcp6275-e/sn: extended temperature, 8ld soic package. b) mcp6275-e/ms: extended temperature, 8ld msop package. c) mcp6275-e/p: extended temperature, 8ld pdip package. d) mcp6275t-e/sn: tape and reel, extended temperature, 8ld soic package. ?
mcp6271/1r/2/3/4/5 ds21810e-page 32 ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. ds21810e-page 33 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of microc hip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, linear active thermistor, mindi, miwi, mpasm , mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2006, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona, gresham, oregon and mountain view, california. the company?s quality system processes and procedures are for its pic ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
ds21810e-page 34 ? 2006 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway habour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7250 fax: 86-29-8833-7256 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - gumi tel: 82-54-473-4301 fax: 82-54-473-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - penang tel: 60-4-646-8870 fax: 60-4-646-5086 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 12/08/06

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